Example embodiments relate to memory devices, and more particularly, to a memory device using error correcting code (ECC) and a system thereof
Resistive memory devices, such as phase change random access memory (PRAM), magnetic RAM (MRAM), and resistive RAM (RRAM), exhibit high-integration capabilities of dynamic RAM (DRAM), non-volatile capabilities of flash memory, and high-speed operations of static RAM (SRAM).
If any one of memory cells included in such a memory device does not operate normally, the memory device cannot appropriately perform an operation thereof. To solve this problem, an error checking operation using ECC may be employed in such a memory device.
However, for example, when memory cells are reset in PRAM, data can be read from the PRAM a predetermined amount of time after the resetting.